The inventive concept relates to a storage device including a multi data rate memory device and a memory controller for same. More particularly, the inventive concept relates to a memory controller for a storage device including a sub controller that controls operations directed to storage blocks having different data rates.
In order to control memories or storage devices having different operating speeds a number of corresponding channels are usually required. The memory controller may include channel interfaces corresponding to the respective channels, where each channel interface may modulate a reference clock signal and transceive signals via connected channels in synchronization with the modulated reference clock signal.
A delay locked loop (DLL) circuit may be used to control a delay line, such that the phase of an input reference clock signal matches phase(s) of feedback signals output through the delay line. A master DLL circuit may detect a lock value corresponding to a lock state and provide the lock value to a slave DLL circuit.